FPGA implementation of Logarithmic Unit

Introduction Implementation of floating point in FPGA (Field Programmable Gate Arrays) is not easy. Paper presents FPGA core implementing these operations by representation of floating point numbers as 32-bit integer (fixed point) logarithm [1]. Basic arithmetical operations are performed in the logarithm numbering system (LNS) suitable for FPGA. Implemented intellectual property core takes just 18% of the XILINX Virtex XCV1000-6 FPGA device and operates at 17MHz. We have implemented MEX library emulating bit-exactly the properties of the final hardware. Therefore, Matlab serves for as simulation and visualization tool for prediction.